Cadence Design Launches Two New Platforms For Massive Chip Designs

by | Apr 17, 2024 | In the News

Cadence has updated its platforms that supports chip design teams, offering more than 2X more capacity and 1.5X faster performance than the previous generation and can support chips up to 48 billion gates.

Designing and testing chips is constantly becoming more difficult, requiring software and emulation hardware that can keep up with the growth in transistors. And of course the emergence of chiplets adds a new dimension. As the challenges grow, so must the hardware used to emulate and debug the chip and prepare the software that will run on the semiconductor once it is back from the fab.

Cadence offers emulation and prototyping hardware to support this iterative development process. The new Palladium Z3 system accelerates hardware verification, and through functional and interface congruency, models can be quickly brought up onto the Protium X3 system for accelerated software validation. It is a Yin and Yang arrangement, or as Cadence calls it, a Dynamic Duo. And both platforms just got a big boost in the latest updates, announced this week at the Cadence Live event in Santa Clara.

The New Cadence Verification Duo

The new Palladium Z3 system uses custom Cadence processors to validate the logic implementation (the gates) of the chip design. Since the platform can support up to 48 billion gates, it can handle a massive chip without breaking it down into smaller blocks. The Protium X3 platform for emulation uses AMD Field Programmable Gate Arrays (FPGAs) to test software on the design validated by the Palladium.


The new Dynamic Duo. Cadence

Nvidia CEO Jensen Huang joined Anirudh Devgan, Cadence CEO on stage at Cadence Live. “Nvidia has the largest installation of Palladium systems in the world. Blackwell would have been impossible without Cadence Palladium. I love Palladium!” exclaimed Huang as he leaped on the stage.


“I Love Cadence!”, Jensen Huang, Nvidia CEO. The Author

The “Dynamic Duo III” provides a unified compile and virtual/physical interface, allowing designers to bring up their designs 3-5 times faster than the previous platforms.

DDIII Slide 3

The Palladium Z3 helps debug the hardware while the FPGA-based Protium X3 emulates the hardware design for software debugging. Cadence

A new modular compiler for both platforms can enable designers to complete compilation in near-constant compile time, which can be critical to keep teams on schedule when building extremely large chips (billions of gates) where traditional compiler approaches could stretch completion into days.

DD III Slide 5

This is huge: For Billion gate-class designs, the Cadence compilers deliver near-constant compile times. Cadence

The Palladium Z3 system now supports domain-specific apps that give users access to a complete suite for managing system and semiconductor design complexity. The domain-specific apps include a 4-State Emulation App, the Real Number Modeling App, and the Dynamic Power Analysis App. The 4-state emulation app can accelerate emulation by se much as 100-fold, while the Digital Mixed Signal emulation app can yield a 500-fold acceleration speed increase.

“With the new 4-State Emulation App, we can accelerate the low-power verification of our complex SoC designs, improving our verification accuracy and low-power coverage while improving overall verification throughput.” Seonil Brian Choi Vice President, Samsung Electronics.

DD III Slide 6

Adding to the hardware, Cadence supports multiple applications that can significantly improve designed productivity. Cadence

“As SoCs become more complex, scalable validation and verification tools that enable massive software testing before tapeout are more critical than ever,” said Tran Nguyen, senior director of design services, Arm. “The latest hardware verification platforms and tools from Cadence are sparking innovation in Arm IP design for AI, automotive, and data center applications and we look forward to how this will benefit our mutual customers.”


As semiconductor industry is supercharged by AI applications, the demand for faster turnaround times and ever-larger chips is driving the EDA industry to deliver better software and hardware, using AI to further accelerate the process. The new Dynamic Duo III seems to fit the bill quite nicely. Both platforms are being used by select customers today, with general availability beginning in Q3 this year. The new modular compiler and apps such as the four-state emulator should further enhance engineering productivity and make it a little easier for engineers to deliver better products, in one tape-out, to meet the needs of a fast growing market place.