Three years ago, EDA vendor Synopsys started helping clients use reinforcement learning, an AI technique, to accelerate and improve physical chip layout with striking results. Physical chip design presents engineers with some 1090000 possible ways to lay out the circuits in silicon, and each alternative has a unique impact on cost and performance. But AI is uniquely well suited to simulate the problem, and estimate the impact of various choices. Early adopters of Synopsys technology gave the new tech, called Design Space Optimization, or DSO.ai, a try and saw a dramatic improvement in Power, Performance, and/or Area (PPA) compared to the traditional approach, and it took far less time as well.
Using AI to Design Chips Moves Into The Mainstream
Since the launch, Synopsys has announced that clients have taped out over 100 chips using the AI tools to improve productivity and produce measurably better chips. Last year, Synopsys added access to its software to the Microsoft Azure cloud, and STMicroelectronics achieved the first-ever commercial design tape-out using the cloud-based tools. The company realized a 3x productivity uplift for power, performance and area (PPA) using Synopsys DSO.ai.
Indavong Vongsavady, Director of STMicroelectronics Methods, Tools, and Infrastructure, described to us how his teams were able to run 1000’s of experiments using DSO.ai on Azure, helping them to find more optimal physical design options and evaluating the impact on PPA. STMicro used DSO.ai on an Arm device they recently taped-out and realized a 3X increase in PPA exploration productivity.
Memory designs are harder to optimize, since memory chips are a regular array of blocks. But even memory designer SK Hynix was able to reduced die size by up to 5% on the most advanced process technologies.
Clearly, AI provides a valuable too to accelerate the design process for semiconductors, helping design teams to improve productivity, evaluate thousands of alternative layouts, and produce better chips in terms of PPA. Very soon, nearly every chip will be designed using AI.