The IBM Telum Processor: Integrated AI for Enterprise Workloads

Aug 23, 2021

IBM’s Next-generation Processor Integrates AI into IBM Z

Transaction processing is the lifeblood of the modern enterprise, and many use IBM® Z for these mission-critical applications. Soon, these enterprises will be able to run accelerated Artificial Intelligence (AI) processing on those systems, providing real-time analytic insights. There are significant potential benefits when applying AI in situ where the data resides, and the transactions are taking place, making it possible to inference every transaction to enrich it with trusted, actionable insights. Today, conducting AI processing during transactions relies on using the Z cores for machine learning or offloading the processing to other servers with GPU accelerators for batch processing. Of course, the latter adds high cost and injects latencies that inhibit real-time analytics and expose an additional security surface to intrusion.

This paper investigates the upcoming Telum processor that IBM previewed at the recent Hot Chips conference, which IBM believes will enable new innovations in the world’s most venerable and stable enterprise computing platform.  You can download this exclusive Cambrian AI research paper by clicking below.

Table Of Contents

  • Introduction
  • Enterprise Applications and AI
  • The New Z Processor with On-Board AI Acceleration
    • Foundation of the Telum Chip: Core and L2 Cache with Cache Persistance
    • Building Large Scale Systems: New Fabric Interconnects up to 32 Chips
    • Integrated AI Accelerator – Integration with Z Processor Cores
    • Integrated AI Accelerator – Computer Arrays and Data Movers
    • Programming the Telum AI Accelerator
    • Enterprise-Class Availability & Security
  • Example Use Cases
  • Performance, Scalability, and Latency
  • Conclusions
  • Figure 1: The IBM Telum Processor Design
  • Figure 2: Foundation of the Telum chip: Core and L2 cache
  • Figure 3: Bigger and faster caches: Horizontal cache persistence
  • Figure 4: Building large scale systems: connecting up to 32 chips
  • Figure 5: Integrated AI Accelerator – integration with Z processor cores
  • Figure 6: Integrated AI Accelerator – compute arrays
  • Figure 7: Seamlessly integrate AI into existing enterprise workload stacks

Companies Cited

  • NXP – Power Architecture
  • Tensorflow
  • PyTorch
  • ONNX
  • Linux