Promising Returns For Suite Of AI Solutions

by | Jul 24, 2023 | In the News

Synopsys is seeing strong demand for its newer AI technologies in test, verification, manufacturing and analog migration, in addition to the ongoing need for design optimization (

Synopsys was the first Electronic Design Automation (EDA) company to provide AI to accelerate the physical design of chips. The company has recently extended this AI approach to other areas of its business, as we reported after the last Synopsys Users Group (SNUG) meeting in April. Now the company shares the benefits its clients have realized using tools for chip testing, verification, and analog migration.

Shankar Krishnamoorthy, GM of Synopsys EDA Group.   r

Shankar Krishnamoorthy, GM of Synopsys EDA Group. Synopsys

“With, the whole is greater than the sum of its parts,” said Shankar Krishnamoorthy, GM of Synopsys EDA Group. “Since the chip development flow encompasses several steps, the more tightly the AI-driven solutions are integrated, the better the outcomes. Using Synopsys AI solutions, customers have seen more than 3x productivity increases and up to 20% better quality of results, with reduced use of overall resources. And we’re just getting started.”

In recent Synopsys announcements, including a July blog, How STMicroelectronics and Microsoft are Using AI-Driven Technology to Optimize PPA, Synopsys is reporting early positive returns from customers using it full suite of AI tools:

  • Nvidia, TSMC, IBM, MediaTek and Renesas all support Synopsys’ AI-driven EDA design strategy with significant benefits already being seen:
  • Microsoft is reducing power dissipation up to 15%
  • Renesas achieves a 10x improvement in reducing functional coverage holes and up to 30% increase in IP verification productivity.
  • STMicroelectronics became the first-ever commercial design tape-out using AI in the cloud, realizing a 3x productivity uplift for power, performance and area (PPA) on Microsoft Azure
  • MediaTek is observing significant test pattern reduction improving overall test time.
  • SK hynix is reducing die size by up to 5% on the most advanced process technologies.
  • The award-winning Synopsys autonomous design system continues to scale with more than 240 commercial tape-outs registered by customers

The Problems and The Opportunities

As we know, AI is making its way into every industry – including the chip design world – and for good reason. AI enables faster processes, improves decision-making, reduces human error, assists with mundane and repetitive tasks, and more. With growing design complexity and shrinking market windows, new approaches in chip design are needed to meet the demand for silicon that can power next-generation data centers, medical tech devices, the latest smartphone models, as well as tackle global issues such as climate change and energy efficiency.

Hardware design costs rise significantly as chip design and manufacturing costs increase with complexity. To manufacture on the most advanced process nodes, designers are seeing 2-3X higher prices than in previous generations. As you can see below, McKinsey & Company says a 5 nm chip costs, on average, $540M to develop and takes 864 engineer days to complete. At this rate of increase, we will quickly see costs spiral toward $1B, putting chip development out of reach of many companies.

Development costs are skyrocketing.

Chip development costs are skyrocketing. Synopsys

Nearly three years ago, Synopsys was the first EDA company to adopt AI in its Design Space Optimization application and customers quickly adopted the reinforcement learning based solution to help speed chip physical design and back-end layout and improve quality of results . Results have been impressive, reducing engineering time from many months to a few weeks. With more than 240 production designs having taped out to manufacturing, using AI for chip design has quickly progressed from a relatively esoteric idea to the new standard.

The suits of AI tools. Synopsys

“Increased complexity, engineering resource constraints and tighter delivery windows are challenging. A full AI-driven EDA software stack can address” Krishnamoorthy added. “With solutions, our customers’ ability to search design solution spaces across multiple domains is in hyperdrive. They’re finding optimal results far faster as the .ai learns run-to-run, and it’s transforming their ability to meet and beat tough design and productivity targets.”





Now, Synopsys and its clients are able to extend the applicability of AI across the chip design flow with, and are able to quantify the improvements over traditional engineering. In the area of verification, a process which identifies and corrects design defects in a chip before it goes into manufacturing, Renesas and other clients have seen quality of results increase with far fewer tests; 1000 tests vs 14,000 tests to achieve the same coverage, for example.

“With our AI-based verification coverage closure and regression analysis testing solution, our customers are seeing very dramatic improvements in time to coverage,” said Krishnamoorthy. “The whole profile of that coverage attainment core dramatically changes because of the power of the reinforcement learning engine.”

Test pattern counts have seen a 20% reduction across multiple clients and design segments which directly translates to direct cost savings with lesser time on the tester.

Growing importance of Analog Design Automation

Today’s designs are commonly comprised of a mix of analog and digital components. How can analog designers keep up with their digital counterparts and quickly progress from node to node? The answer lies in automation and AI.

The ability to rapidly migrate from one process node to another, or between nodes from different foundries, is one way to keep supplies flowing while optimizing PPA. This is easier said than done on the analog side, where node migration can be a manual, time-consuming endeavor.

However, AI and automation can address some of the design and verification challenges of the analog world, preventing an analog bottleneck that could potentially stifle the entire design. Many of our customers are excited to start using the Synopsys Analog Design Optimization Solution for rapid migration across process nodes in an automated flow, with AI-driven features, that save time and effort in the continued drive to meet demands for high-performing silicon chips.

And testing costs have seen a 20% reduction in costs across multiple clients and design segments. Analog Design is the newest area where AI has shown superior results versus the normal processes. Specifically, Synopsys clients have been able to automate much of the work need to migrate an analog design schematics and layouts to new manufacturing processes.


Synopsys has led the EDA field in the deployment and adoption of AI to accelerate chip design and lower costs by automating time-consuming activities, freeing up design engineers to focus on the more demanding task of design innovation. Customers can produce better chips at a lower cost by extending Synopsys reinforcement learning tools across the design stack. Since the chip development flow encompasses several steps, the more tightly the AI-driven solutions are integrated, the better the outcomes.