I won’t start this blog by talking about Chat GPT. You’re tired of hearing about it, right? But the same technology (reinforcement learning) is accelerating change in the world of Electronic Design for chips and chiplets, led by EDA companies Synopsys and more recently Cadence Design. AI can augment or replace the drudgery that electrical engineers often contend with, and produce better chips faster with far fewer engineering resources.
Synopsys.ai
As we have previously reported, Synopsys jumped out to an early lead nearly three years ago with DSO.ai. Synopsys.ai is a suite of AI-driven solutions for the design, verification, testing, and manufacturing of the most advanced digital and analog chips. It is the industry’s first full-stack, AI-driven EDA suite for chipmakers. Synopsys.ai provides AI-driven solutions for chip design, with digital and analog, verification, test and manufacturing components.
Here are some of the specific AI-driven solutions that are available in Synopsys.ai:
- Design Space Exploration (DSO.ai): DSO.ai is an AI-powered tool that helps engineers to explore the design space of a chip and find the optimal solution for their needs.
- Verification (VSO.ai): VSO.ai is an AI-powered tool that helps engineers to verify the correctness of a chip design.
- Test (Test.ai): Test.ai is an AI-powered tool that helps engineers to generate test programs for chips.
- Manufacturing (Manufacture.ai): Manufacture.ai is an AI-powered tool that helps engineers to optimize the manufacturing process for chips.
Some of the key benefits of using Synopsys.ai include:
- Increased productivity: Synopsys.ai can automate repetitive tasks, such as design space exploration and verification, freeing up engineers to focus on more creative and strategic work.
- Improved quality: Synopsys.ai can help to identify and fix design errors earlier in the process, leading to higher quality chips.
- Reduced time to market: Synopsys.ai can help to shorten the design cycle, getting chips to market faster.
Synopsys claims its AI engines can significantly boost engineering productivity and silicon quality while minimizing costs. Let’s take a look.
Close-up of sign with logo at Silicon Valley headquarters of technology company Synopsys, Mountain View, California, May 3, 2019. (Photo by Smith Collection/Gado/Getty Images) Getty Images
Customer Results Using Synopsys.ai
DSO.ai, Synopsys’ first AI driven product, has already been used to tape out over 200 commercial chips with dramatic results. While the first version was great, the company has continued to improve the AI model and enable design teams to lower power by an additional 5% and improve computational efficiency by 50% while delivering a solution 30% faster.
DSO.ai continues to improve time needed for physical chip design. Synopsys
Synopsys shared the benefits of one of the newest AI tools, the Test Space Optimization tool, or TSO.ai at the SNUG event. In four different chips, customers reported an average of over 20% reduction in test patterns required to meet quality criteria. And of course the saving are dramatic, since each and every chip needs to be tested before being sold to a customer.
Synopsys sees from 17-60% fewer patterns being needed for testing, thanks to AI. Synopsys
In the Design Verification space, VSO.ai has shown significant benefits as well, requiring less than 1/3rd the number of tests needed to to achieve 100% coverage. This can have a dramatic impact on the time to market for a new chip.
Verification Space Optimization (VSO.ai) shows dramatic reduction in the number of passes needed to reach 100% coverage. Synopsys
Conclusions
If you are a chipmaker looking to improve your design process, AI is a powerful tool that can help you get to market faster with a better product. The results speak for themselves. Synopsys has fleshed out its portfolio of AI tools, and has reported on actual improvements in customer design workflows. After seeing these results, it is hard to imagine anyone would not adopt Syniopsys.ai.