The semiconductor industry has been applying AI to accelerate chip design for over three years, achieving 10X productivity gains and focusing primarily on tasks that now seem relatively easy, such as floor-plan optimization using massive recurrent neural networks. But capturing a design team’s intentions and understanding the tradeoffs needed to meet the business goals of a chip has remained beyond reach, until now.
The Problem is Huge
Chip design capacity demand has grown rapidly, but unfortunately, the pool of engineers needed has not kept pace. This problem has primarily been driven by students’ focus on higher-paying jobs such as software and, more recently, AI roles, a trend that is not easy to address. Cadence Design, a client of Cambrian-AI Research, estimates that industry revenue will reach a trillion dollars by the end of the decade, but only if 270,000 engineers are hired above current hiring trends to handle increasingly complex designs.
But an alternative to convincing students to study hardware engineering could be to use AI to augment the engineers we already have and will hire.
The AI Design Automation Journey
AI design products from the three EDA leaders (Cadence, Siemens, and Synopsys) typically cover early stages of design optimization, spanning synthesis, place-and-route, and physical design, and help users resolve problems using natural language, reducing the workload for experienced engineers by leveraging their expertise. Designers using leading-edge digital SoCs at top foundry nodes (e.g., 5/4/3 nm) apply AI to approximately 20–40% of new designs, with some AI assistance for floor planning or macro placement using products such as Cadence Cerebrus or Synopsys DSO.ai.
The Journey to Autonomous Chip Design, still many years away, has five major phases. CADENCE DESIGN
Cadence Introduces The ChipStack AI Super Agent
Cadence, seeing an opportunity to lead in AI for design automation, acquired ChipStack last November and has already integrated its technology into the Cadence JedAI database platform, with testing underway with users.
Cadence has now launched the ChipStack AI Super Agent, the world’s first agentic workflow for automating chip design and verification. It provides up to 10X productivity improvements for coding designs and test benches. It creates test plans, orchestrates regression testing, debugs issues, and automatically fixes them.
“ChipStack represents a major leap in our design-for-AI and AI-for-design strategy, applying agentic AI directly to our customers’ front-end flows to tackle the growing complexity and scaleof modern chips,” said Anirudh Devgan, president and CEO, Cadence.“By leveraging intelligent agents that autonomously call our underlying tools, we are enabling dramatic productivity gains for our customers in critical design and verification tasks while freeing scarce engineering talent to focus on innovation.”
The ChipStack acquisition last year quickly vaulted Cadence into the lead for applying Agentic AI to chip design. CADENCE DESIGN
This sounds like science fiction, but Cadence has already tested the platform with key customers, who have given it rave reviews. “As semiconductor complexity continues to accelerate, AI has become essential to designing the next generation of chips,” says Timothy Costa, GM of Industrial and Computational Engineering at NVIDIA. “Our collaboration with Cadence, including innovations like the Chip Stack Al Super Agent, demonstrates how combining intelligent reasoning capabilities such as Mental Models and automated formal test plan generation with NVIDIA accelerated computing can unlock new levels of productivity and efficiency for chip (design).”
The Key To Agentic Chip Design: The Mental Model
One reason it has taken a while to develop design and verification AI automation is the complexity of the team’s design intent. The Mental Model handles the specification of behavior, operational relationships, design hierarchy and specifications. Once a design team gets this right, it can then iterate on verification and implementation.
The ChipStack approach has designers start by defining a Mental Model of their chip ambitions. CADENCE DESIGN
The Super Agent suite iterates what to test and how, writes a test bed and orchestrates with Cadence EDA design tools to produce a design, results, and metrics. It even suggests debug hints for failures.
Once the design is understood by the Mental Model, an iterative approach is used to design and verify it. CADENCE DESIGN
The ChipStack AI Super Agent supports both cloud-based and on-premises frontier models, including NVIDIA’s NeMo generative AI framework and the NVIDIA Llama Nemotron Reasoning Model, to improve designer productivity. This continues to advance the vision of a true “silicon agent,” spanning the many disciplines and workflows required to deliver the next generation of chips.
The Net-Net
While we have yet to achieve the holy grail of using AI to automate chip design, the ChipStack AI Super Agent solution will be another game-changer as companies race to deliver better chips faster. And in this case, faster means cheaper. Cadence is the first EDA company to breach this barrier, but it will undoubtedly not be the last.
Game on.
Disclosures: This article expresses the opinions of the author and is not to be taken as advice to purchase from or invest in the companies mentioned. My firm, Cambrian-AI Research, is fortunate to have many semiconductor firms as our clients, including Baya Systems BrainChip, Cadence, Cerebras Systems, D-Matrix, Esperanto, Flex, Groq, IBM, Intel, Micron, NVIDIA, Qualcomm, Graphcore, SimA.ai, Synopsys, Tenstorrent, Ventana Microsystems, and scores of investors. I have no investment positions in any of the companies mentioned in this article.